The present invention relates to integrated circuits including power and logic transistors on the same chip. It more particularly relates to an integrated circuit including a VDMOS power transistor, lateral MOS logic transistors and means for supplying a bias voltage to a gate electrode of the VDMOS transistor, and to a method of forming same.
FIG. 1 is a schematic section view of an integrated circuit described in European Application 87/00325.4 in the name of Thomson CSF. For the sake of simplicity only certain elements of this structure are illustrated (particularly certain thin and thick oxide layers are not shown). In the right-hand portion of FIG. 1 is an illustration of a cell of a power VDMOS (vertical diffused MOS) transistor 1 of the enhanced type and in the left-hand portion of the figure are represented logic components such as a depleted N-channel lateral MOS transistor 2 and an enhanced N-channel lateral MOS transistor 3.
This structure is made on a substrate comprising an N-type layer 10 epitaxially grown on an N.sup.+ -type silicon wafer 11.
In a first doping step are formed P-type regions 12, especially corresponding to wells wherein the logic portion of the chip is formed.
In a second doping step, P.sup.+ regions with a high doping level are formed, this doping level being high enough to obtain ohmic contacts with metallizations. The P.sup.+ regions enable an ohmic contact with well 12 and regions 18 of the power VDMOS transistor to be formed to obtain contact with a so-called "bulk" region in an upper region where the channel is formed.
In a third doping step are formed N-type regions 13 especially corresponding to channel regions of the depleted lateral MOS transistors.
Then, one conventionally forms (for example through oxidation, deposition of polycrystalline silicon, etching and reoxidation) gates 21 of the power transistor, gates 22 of the enhanced lateral MOS transistors and gates 23 of the depleted lateral MOS transistors. Gates 21 and 22 are simultaneously formed during this step.
A fourth P-type doping step in the region of the VDMOS transistor forms the channel regions 30 of those transistors with the gate regions acting as a mask.
Then, in a fifth doping step, one forms, by using the above-mentioned gates as a mask, N.sup.+ regions especially corresponding to the sources 32 of the power transistor and to the sources and drains 33-36 of the depleted and enhanced lateral MOS transistors.
Lastly, after oxidation and opening of appropriate windows, one forms a metallization layer wherein one etches the source metallization 41 of the power transistor and the source and drain metallizations 42-45 of the lateral transistors as well as other metallizations such as contact metallizations 46 of the wells wherein are formed logic components.
The rear surface of the component which corresponds to the drain of the VDMOS transistor 1 is coated with metallization 48.
In operation, such a structure is generally connected so that its rear surface 48 is at the highest positive voltage (+V.sub.HT), all the other metallizations being at lower voltages and the metallization 46 of well 12 being usually grounded.
The above described structure is particularly advantageous due to its simplicity. Indeed, it requires a minimum number of masking and doping steps. As seen previously, only five doping types are used. However, this simplicity enables only a limited number of components to be realized in such a structure.
The user usually desires, while maintaining the low cost and reliability associated therewith, to have additional elementary components, such as for example PN diodes that are biased to operate in the forward direction (conductive with a voltage on the P region higher than the voltage on the N region).
More specifically, it is often desired to obtain a reference voltage from the voltage of the rear surface V.sub.HT to control the gate of the enhanced VDMOS transistor, for example. This problem has already been discussed for example in U.S. Pat. No. 4,792,840 granted on Dec. 20, 1988 to Bruno Nadd and assigned to Thomson-CSF. When the invention of this patent was made, forming a Zener diode on a structure of the above described type was thought to be practically impossible. The Nadd patent specifically states: "Clipping by means of the Zener diode is difficult to obtain because of the difficulty of integrating this element" (column 2, lines 33-35).
To solve this problem, the above patent suggests applying the high voltage supplied to the lower surface of the chip to the upper chip surface through an N.sup.+ diffusion and then distributing this high voltage through a spiral resistor.
This method gives satisfactory results but has the drawback of requiring a large silicon surface. Moreover, as mentioned, this method does not permit derivation of a reference voltage inside the chip; instead the reference voltage is the result of a voltage division through a resistor bridge.
Thus, an object of the invention is to provide a new and improved means for obtaining on the upper surface of an integrated circuit chip the same voltage as is available on the lower surface of the chip.
Another object of the invention is to obtain a reference voltage on the upper surface of an integrated circuit chip from the high voltage available on the lower surface wherein the number of steps necessary to form the chip is not increased.
A further object of the invention is to provide a new and improved integrated circuit chip including a reference voltage source without involving substantial current consumption.
An additional object of the invention is to provide a new and improved integrated circuit chip including a power VDMOS and logic circuit elements wherein a reference voltage is derived on an upper face of the chip and to a method of making same such that the number of steps to form the chip is not increased over the number of steps required to form the chip without the reference voltage on the upper face.